Novel self aligned channel implant, elevated S/D process by gate electrode damascene

ABSTRACT

A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the SID regions a gate electrode has been created with elevated SID regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing SID implant a gate electrode has been created with elevated SID regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing SID implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention belongs to the field of semiconductormanufacturing, and more specifically to a method for the implantation ofa self-aligned channel and elevated source/drain areas in the damasceneprocess.

[0003] (2) Description of the Prior Art

[0004] Self-alignment is a technique in which multiple regions on thewafer are formed using a single mask, thereby eliminating the alignmenttolerances that are required by additional masks. As circuit sizesdecrease, this approach finds more application. One of the areas wherethe technique of self-alignment was used at a very early stage was theself-aligned source and gate implant to the poly gate.

[0005] The present invention relates to the Damascene process that isused for the formation of semiconductor devices. Damascene derives itsname from the ancient art involving inlaying metal in ceramic or woodfor decorative purposes. In Very Large-Scale Integrated circuitapplications, the Damascene process refers to a similar structure.

[0006] The Damascene process has been demonstrated on a number ofapplications. The most commonly applied process is first metal or localinterconnects. Some early Damascene structures have been achieved usingReactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP)is used exclusively today. Metal interconnects using Damascene of copperand Of aluminum is also being explored.

[0007] As transistor dimensions have decreased, the conventional contactstructures used began to limit device performance. It was, for instance,not possible to minimize the contact resistance if the contact hole wasalso of minimum size while problems with cleaning small contact holesalso became a concern. In addition, the area of the source/drain regionscould not be minimized because the contact hole had been aligned to thisregion using a separate masking step whereby extra area had to beallocated to accommodate misalignment. It was also practice to useseveral, small contact holes of identical size meaning that the fullwidth of the source/drain region was not available for the contactstructure. This resulted in the source/drain resistance beingproportionally larger than it would have been in a device having minimumwidth.

[0008] One of the alternate structures that have been employed in aneffort to alleviate this problem is the formation of self-alignedsilicides on the source/drain regions. Where these silicides are formedat the same time as the polycide structure, this approach is referred toas a salicide process. The entire source/drain region (of, for instance,a CMOS device) is contacted with a conductor film. This approach becomeseven more attractive where such a film can be formed using aself-aligned process that does not entail any masking steps.

[0009] Although CMOS is now a dominant integrated circuit technology, itwas in its initial phases considered to be only a runner up for thedesign of MOS IC's. The CMOS design is based on the paring ofcomplementary n- and p-channel transistors to form low-power IC's. CMOStechnology has, over the years, developed to the point where it nowoffers advantages of significantly reduced power density anddissipation, as well as in device/chip performance, reliability, circuitdesign and fabrication cost.

[0010] In advanced CMOS processes, the gate length are short enough thatLightly Doped Drain (LDD) structures must be used to minimizehot-electron effect, especially if the devices are NMOS devices. Aremovable spacer LDD process has been explored that does not requiredthe use of any masks other than the two needed to selectively form thesources and drains of the two transistor types.

[0011] Various techniques have been developed for forming the shallowsource/drain junctions that are needed for sub-micron CMOS devices. Onesuch approach uses As for the n-channel devices while BF₂ ⁺ is used forthe p-channel devices. Another approach applies the formation of COSi₂(before the formation of the source and the drain regions) by means ofheavy ion implantation. Yet another approach uses the creation ofso-called elevated source-drains. A thin (for instance 200 um.)epitaxial layer of silicon can be selectively deposited onto the exposedsource/drain areas of the MOS transistor, this following theimplantation of the lightly doped region of the LDD structure and theformation of the spacers. This process leads to the formation of heavilydoped, shallow source/drain regions. The source/drain junction depth isthis case are less than 0.2 um. The gate oxide that covers thesource/drain regions is usually etched away and re-grown following theimplant step required to for the elevated regions.

[0012] The method by which components of an integrated circuit areinterconnected involves the fabrication of metal strips that runs acrossthe oxide in the regions between the transistors, the field regions.However, these metal strips form the gates of parasitic MOS transistors,with the oxide beneath them forming a gate oxide and the diffusedregions acting as the source and drain regions. The threshhold voltageof these parasitic transistors must be kept higher than any possibleoperating voltage so that spurious channels will not be inadvertentlyformed between devices. Several methods have been used to raise thethreshold voltage. These methods involve increasing the field oxidethickness or raising the doping beneath the field oxide. The large oxidestep however presents problems of step coverage so that reduced oxidethickness is preferred. The doping under the field oxide must thereforebe increased. Emphasis is nevertheless still placed on making the fieldoxide seven to ten times thicker than the gate oxide, this heavy layerof oxide also reduces the parasitic capacitance between the interconnectrunner and the substrate. Normally, ion implantation is used to increasethe doping under the field oxide. This step is called the channel stepimplant. The combination of channel-step-implant with the thick oxidecan provide adequate isolation for oxide isolated bipolar IC's.

[0013] In the deep sub-quarter micron CMOS process, Prior Art uses a(super) steep channel profile in order to maintain good current driveand high immunity against leakage current and voltage penetration. Thisapproach however increases the CR delay time due to the incurred highsource to drain capacitance. The increase of the CR delay time can beavoided if the implant is located directly below the transistor gate.The challenge when combining salicide technology with source/drainimplantation is to achieve a shallow junction for the sub-quarter micronCMOS process. Elevated source/drain regions maintain good resistivitycharacteristics for the salicide process while at the same timeproviding shallow source/drain junctions. The critical step in applyinggate photolithography typically is the step of exposing the source/draingate, within the process of the present invention the requiredtolerances for this processing step can be relaxed since the size of thesource/drain gate electrode has been increased.

[0014] U.S. Pat. No. 5,434,093 (Chau et al.) shows a self-alignedchannel implant, elevated s/d process by gate electrode damascene.However, this patent differs from the invention in the exact order ofthe LDD I/I. This patent is very close-to the invention.

[0015] U.S. Pat. No. 5,538,913 (Hong) Process for fabricating MOStransistors having full-overlap lightly doped drain structure—showsself-aligned channel implant, (not elevated) s/d process by gateelectrode damascene. This patent does not show the invention's trenchinto the substrate. This patent is extremely close to the invention.

[0016] U.S. Pat. No. 5,801,075 shows a self aligned channel implant,elevated s/d process by gate electrode damascene. However, this patentdiffers from the invention by not showing an angled LDD I/I.

[0017] U.S. Pat. No. 5,376,578(Hsu et al.) teaches a FET with raiseddiffusions. However, this reference differs from the invention.

[0018] U.S. Pat. No. 5,786,256(Gardner et al.) recites a damascene gateelectrode process. However, this reference differs from the invention inthe exact 1/1 steps.

SUMMARY OF THE INVENTION

[0019] It is an objective of the present invention to create elevatedsource/drain regions by etching into the underlying substrate therebymaintaining good resistivity characteristics for the salicide processwhile at the same time providing shallow source/drain regions.

[0020] It is another objective of the invention to provide a gateelectrode structure with disposable spacers thereby facilitating theimplanting of the Lightly Doped Drain (LDD) and Source/Drain (S/D)regions.

[0021] It is another objective of the invention to provide a gateelectrode structure wherein the gate polysilicon is above the gatespacers thereby facilitating the process of surface silicidation.

[0022] It is another objective of the invention is to provide a methodto create a deep channel implantation for CMOS devices to improve devicespeed and without mask alignment problems.

[0023] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices whilemaintaining good device electrical insulation characteristics.

[0024] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices withoutincreasing device CR delay time.

[0025] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices whereinthe implantation is located directly beneath the device gate electrode.

[0026] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices whilemaintaining shallow junction depth on the top surface of thesource/drain regions.

[0027] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices whilemaintaining low sheet resistance in the silicon substrate.

[0028] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMOS devices therebymaking alignment tolerances for the photo lithographic exposing andetching of the device gates less critical.

[0029] It is another objective of the present invention to provide amethod to create a deep channel implantation for CMQS devices for thesalicide process.

[0030] Under the first embodiment of the present invention, the presentinvention teaches forming a thin dielectric layer on top of the siliconsubstrate; a thick layer of oxide is deposited over this dielectric. Anopening is exposed and etched through the layer of oxide, through thethin dielectric layer and into the underlying silicon substrate. Thetrench that is formed in this way in the substrate is shallow, a thinoxide layer is formed on the bottom of this shallow trench in thesubstrate followed by the channel implant, LDD formation and a pocketimplant. Spacers are formed on the sidewalls of the trench, the thinlayer of oxide at the bottom of the trench is removed and replaced witha gate dielectric. The trench is filled and planarized to form the gateelectrode. The thick layer of oxide surrounding the trench together withthe thin dielectric layer on the surface of the silicon substrate areremoved followed by the final step of implanting the source and drainregions.

[0031] Under the second embodiment of the present invention, the presentinvention teaches forming a thin dielectric layer on top of the siliconsubstrate; a thick layer of oxide is deposited over this dielectric. Anopening is exposed and etched through the layer of oxide, through thethin dielectric layer and into the underlying silicon substrate. Thetrench that is formed in this way in the substrate is shallow, a thinoxide layer is formed on the bottom of this shallow trench in thesubstrate followed by the formation of the spacers on the sidewalls ofthe trench after which the channel implant is performed. The thin layerof oxide on the bottom of the trench is removed and replaced with a gatedielectric, the gate electrode is formed. The heavy layer of oxide andthe thin dielectric layer on the surface of the silicon substrate areremoved; the source and drain regions are implanted. Silicide is formedon top of the source and drain regions and on the top surface of thegate electrode. The spacers are removed from the gate electrode followedby the implantation of the LDD in the surface of the substrate where thespacers previously contacted this surface.

[0032] Under the third embodiment of the present invention, the presentinvention teaches forming a thin dielectric layer on top of the siliconsubstrate; a thick layer of oxide is deposited over this dielectric. Anopening is exposed and etched through the layer of oxide, through thethin dielectric layer and into the underlying silicon substrate. Thetrench that is formed in this way in the substrate can be deeper thatthe trench formed under the first and second embodiment of theinvention, a thin oxide layer is formed on the bottom of this trench inthe substrate followed by the channel implant. The third embodimentdiffers from the first embodiment in that no LDD and pocket implantoccurs at this time. Spacers are formed on the sidewalls of the trench,the thin layer of oxide is removed from the bottom of the trench, thegate dielectric is formed at the bottom of the trench followed by theformation of the gate electrode. The spacer formed on the sidewall ofthe trench is overetched so that the top surface of the spacer is lowerthan the top surface of the gate electrode. This enhances the formationof silicide later in the process. The S/D implant is performed, sincethe trench that has been etched into the surface of the siliconsubstrate is relatively deep, most of the SID area is above the gatedielectric. Lateral diffusion of the implant will cause the implant toalso reach the regions under the gate electrode spacers, this lateraldiffusion takes the place of previous LDD implant. The formation ofsilicide will take place on the top surface of the gate electrode andthe regions of the surface of the silicon substrate above the SIDregions.

[0033] The structures obtained under the three embodiments of thepresent invention are not identical. These structures however meet theobjectives of the present invention as highlighted above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 shows a cross-section of the silicon substrate after thedeposition of the thin dielectric layer and the deposition of the heavylayer of oxide for the first, second and third embodiment of theinvention.

[0035]FIG. 2 shows a cross-section after formation of a trench under thefirst, second and third embodiment of the invention.

[0036]FIG. 3 shows a cross-section after formation of the oxide on thebottom of the trench and during the channel implant, LDD and pocketimplant under the first embodiment of the invention.

[0037]FIG. 4 shows a cross-section after the spacer, gate dielectric andgate electrode have been formed under the first embodiment of theinvention.

[0038]FIG. 5 shows a cross-section after the heavy layer of oxide andthe dielectric layer have been removed and during the source/drainregions implant under the first embodiment of the invention.

[0039] The above sequence of FIGS. 1 through 5 presents the firstembodiment of the present invention. FIGS. 6 through 9 show the secondembodiment of the invention.

[0040]FIGS. 1 and 2 remain, for the second embodiment of the invention,as shown above under the first embodiment of the invention and apply tothe second embodiment of the invention.

[0041]FIG. 6 shows a cross-section after the formation of the layer ofoxide at the bottom of the trench, the formation of spacers and theformation of the gate dielectric at the bottom of the trench and duringthe implantation of the channel under the second embodiment of theinvention.

[0042]FIG. 7 shows a cross-section after the removal of the layer ofoxide from the bottom of the trench, the formation of the gatedielectric and the formation of the gate electrode under the secondembodiment of the invention.

[0043]FIG. 8 shows a cross-section after the removal of the heavy layerof oxide and the thin dielectric layer from the surface of the substrateand during the SID implant under the second embodiment of the invention.

[0044]FIG. 9 shows a cross section after the silicide has been formed ontop of the SID regions, the spacer has been removed and during theformation of the LDD regions under the second embodiment of theinvention.

[0045]FIGS. 10 through 13 show the third embodiment of the presentinvention.

[0046]FIGS. 1 and 2 remain as shown above under the first and secondembodiment of the present invention and apply to the third embodiment ofthe invention.

[0047]FIG. 10 shows a cross-section after the formation of the layer ofoxide at the bottom of the trench and the implant of the channel underthe third embodiment of the invention. It is to be noted that the depthof the penetration of the trench into the surface of the semiconductorsubstrate is significantly larger than the penetration created under thefirst and second embodiment of the invention.

[0048]FIG. 11 shows a cross-section after the gate spacer has beenformed, the layer of dielectric has been removed from the bottom of thetrench, the gate dielectric and the gate electrode have been formedunder the third embodiment of the invention.

[0049]FIG. 12 shows a cross-section after the removal of the heavy layerof oxide and the thin dielectric layer from the surface of the substrateand after the S/D implant has been performed under the third embodimentof the invention.

[0050]FIG. 13 shows a cross section after the silicide has been formedon top of the SID regions and on the top surface of the gate electrodeunder the third embodiment of the invention under the third embodimentof the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0051] Referring now specifically to FIG. 1, there is shown a crosssection of the silicon substrate 10, a thin layer 12 of oxide formed ontop of substrate 10 over which a layer 14 of silicon nitride isdeposited. The two layers 12 and 14 together form a dielectric. A thicklayer 16 of oxide is deposited on top of this dielectric layer.

[0052] For the deposition of the thin layer 12 of oxide, Low PressureCVD is the preferred deposition technology because of the highdeposition rates and the excellent film thickness uniformity.

[0053] The thin layer 12 of oxide is typically deposited to a thicknessof between 20 and 500 Angstrom. The method of deposition is furnaceoxide deposition or CVD oxide deposition. Layer 12 serves as a stressrelease between the silicon substrate (10) and layer 14 of siliconnitride.

[0054] Layer 14 is an etch stop layer, it is typically deposited to athickness of between 50 and 500 Angstrom, used for layer 14 can be SiNor SiO_(x)N_(y). This layer can be deposited using a thermal or CVDdeposition process.

[0055] Layer 16 is a thick layer of oxide, it is typically deposited toa thickness of between 200 and 3000 Angstrom. It is deposited by eitherCVD or SOG techniques.

[0056]FIG. 2 shows a cross section after the trench 22 patterning andetching has been completed. The trench is patterned and etched using awidened poly pattern, that is a pattern wide enough that electrodespacers and the gate electrode can be accommodated in the trench. Thewider gate makes the silicidation easier since silicidation typicallyexhibits the line-width effect, that is increased junction leakagecaused by the silicide in the source/drain regions while, to form asilicide, a substantial portion of the Si from the junction is consumed.This line-width effect becomes more of a problem as the line width ofthe device shrinks. The etch is an etch through the thick layer 16,through dielectric 24 and into the substrate 10. The etch forms a small,shallow trench 26 in the substrate 10.

[0057] The width of trench 22 is typically in excess of 0.15 um and isdetermined by the width of the gate electrode.

[0058] Typical separation between the source and the drain region of thegate electrode is 0.2 um. This separation follows from a typicalphysical gate length of 0.10 um and a spacer width of 0.05 um.

[0059] The shallow trench 26 is typically between 100 and 1500 Angstromdeep.

[0060]FIGS. 3, 4 and 5 show the first embodiment of the presentinvention.

[0061]FIG. 3 shows a cross section after the formation of a thin oxidelayer at the bottom of the shallow trench 26. The channel implant 36 hasbeen completed creating the channel stop area 34 under the thin oxidelayer 32. Also completed is the LDD 38 and the pocket implant. It is tobe noted that the LDD implant 38 is performed under an angle, this angleof the implant provides an implant “shadow” whereby the LDD implant andionization 38 will affect only the extreme corners under the shallowtrench 26.

[0062] During the channel implant, layer 16 (FIG. 3) shadows the implant38. As a consequence, only the areas under the corners of the bottom ofthe trench 26 (areas 52, FIG. 4) will accept the LDD implant 38.

[0063] Hot-carrier effects cause unacceptable performance degradation inCMOS devices that are built with conventional drain structures if theirchannel lengths are less than 2 um. To overcome this problem, LightlyDoped Drains (LDD) are used. The structures absorb some of the potentialinto the drain and thus reduce the maximum electric field EM. In the LDDstructure, the drain is formed by two implants. One of these isself-aligned to the gate electrode, and the other is self-aligned to thegate electrode on which two oxide sidewall spacers will be formed. Thepurpose of the lighter dose is to form a lightly doped section of thedrain at the edge near the channel. The EM is reduced by this structurebecause the voltage drop is shared by the drain and the channel, this incontrast with a conventional drain structure in which almost all of thevoltage drop occurs across the lightly doped channel region.

[0064] Channel implant typically uses arsenic (As), antimony (Sb),boron, borofluoride (BF₂), indium (In), phosphorus (P).

[0065] Typical implant conditions are as follows: P-well implant: boronenergy: 100 to 220 keV dose: 1e13 to 1e14 atoms/cm² boron energy: 5 to40 keV dose: 1e12 to 5e13 atoms/cm² indium energy: 50 to 250 keV dose:1e12 to 1e14 atoms/cm² N-well implant: P energy: 300 to 600 keV dose:1e13 to 5e14 atoms/cm² P energy: 50 to 300 keV dose: 1e12 to 5e13atoms/cm² As energy: 50 to 200 keV dose: 1e12 to 1e14 atoms/cm²

[0066] The channel implant typically penetrates between 0.02 and 1.5 um.

[0067] The LDD is typically performed as follows: For NMOS: As energy 1to 10 keV dose 1e14 to 1e16 atoms/cm² For PMOS: BF₂ energy 1 to 10 keVdose 1e14 to 5e15 atoms/cm²

[0068] The indicated pocket implant establishes a high punch throughvoltage that results in a low off-state current. Typical operatingconditions for the pocket implant are as follows: For NMOS: In energy 50to 250 keV dose 5e12 to 1e14 atoms/cm² For PMOS: As energy 50 to 250 keVdose 5e12 to 1e14 atoms/cm²

[0069]FIG. 4 shows the formation of the spacer 42, the removal of theoxide from the bottom of the trench, the formation of the gatedielectric 44 and the gate electrode 46.

[0070] Typical operating conditions for these three steps are asfollows:

[0071] Spacer 42 can be formed using thermal S_(i)N or by CVD S_(i)N orby thermal SiO_(x)N_(y) or by CVD SiO_(x)N_(y).

[0072] Gate dielectric 44 can be formed RTO oxide or by JVD oxide or byRTP S_(i)N or by RTP SiO_(x)N_(y) or by JVD T_(i)O₂ or by JVD TaO2.

[0073] Gate electrode 46 can be formed by CVD and/or poly Si or SiGe.

[0074] Spacer 42 typically is between 250 and 1500 Angstrom thick.

[0075] It is to be noted that the thin layer of oxide at the bottom ofthe trench is removed only after the spacer has been formed resulting inthe remaining presence of this oxide in the extreme corners 32 and underspacer 42. The gate dielectric 44 is formed after the spacer has beenformed and is therefore present on the bottom of the trench and betweenthe spacer.

[0076] The spacers have been etched with a slight overetch, the spacerheight is therefore slightly less than the height of the poly. For polygate a thickness of 2000 Angstrom and a deposited oxide film thicknessof approximately 2200 Angstrom, spacer width of 1000 Angstrom aretypically obtained.

[0077]FIG. 5 shows the final structure of the gate electrode within thefirst embodiment of the present invention. The thick oxide layer 16(FIG. 4) is etched away. This etch is patterned with a wet or dilutedHF, BOE RIE process designed to produce a poly feature with verticalsidewalls. The dielectric layer 24 is also etched away. The thindielectric layer 24 (FIG. 4) is also removed.

[0078] The n⁻ implant 52 is the LDD that is formed by the implantation38 (FIG. 3). This implant, also called the graded drain or tip implant,can be carried out with phosphorous to form the lightly doped region ofthe S/D regions.

[0079] The source/drain implant 56 is performed as follows, this implantforms the S/D regions 54.

[0080] Conditions for implant 56 are as follows: For n⁺/p⁺ NMOS: Asenergy: 15 to 100 keV dose: 1e14 to 5e16 atoms/cm² P energy: 10 to 100keV dose: 1e16 to 5e16 atoms/cm² Conditions for the doping are asfollows: For PMOS: B energy: 1 to 50 keV dose: 1e13 to 1e16 atoms/cm²BF₂ energy: 5 to 180 keV dose: 1e13 to 1e16 atoms/cm²

[0081] The n⁻ region at this time is essentially self-aligned to thegate electrode. After the n⁻ implant, a high dose n⁺ implant isperformed with a high current implanter. Typically, arsenic is implantedat a dose of about 5×10¹⁵ cm⁻² and at energies of 40-80 keV. This formsthe low-resistivity drain region 54, which is merged with a lightlydoped n⁻ region. Because the spacer serves as a mask for the As implant,the heavily doped n⁻ region is self-aligned to the sidewall spacer edgesand is thus offset from the gate edge. Since the edge of the n⁺ regionsis further away from the channel than would have been the case in theconventional drain structure, the depth of the heavily doped region ofthe drain can be made somewhat greater without adversely affecting thedevice operation. The increased junction depth lowers both the sheetresistance and the contact resistance of the drain.

[0082] At this point in the processing sequence the gate electrodestructure within the first embodiment of the present invention iscomplete. Created has been a device with an elevated source/drainstructure and a gate with a self-aligned channel implant. The elevatesource/drain structure prevents the consumption of silicon duringsilicidation and is therefore a major advantage of the structure of thepresent invention.

[0083]FIGS. 6, 7, 8 and 9 show the second embodiment of the presentinvention. The processing steps as detailed under FIGS. 1 and 2 applyalso the second embodiment of the present invention, it is assumed thatthe explanations previously provided for FIG. 1 and FIG. 2 precede thefollowing explanations.

[0084] Referring now specifically to FIG. 6, there is shown a crosssection of the trench 22 for the gate electrode, the formation of a thinlayer 72 of oxide at the bottom of the trench 22 that has been etchedinto the silicon substrate 10, the completion of (deposition and etch)the spacer 64 and the implant 66 of channel stop.

[0085] Referring now to FIG. 7, there is shown a cross section of theformation of the gate dielectric 71 and the creation (deposition andetch/planarization) of gate electrode 71. The layer of oxide 72 (FIG. 6)has, prior to the formation of the gate electrode, removed from thebottom of the trench between the spacer, the gate dielectric 71 has beenformed between the spacer and overlying the bottom of the trench.Corners 70 of the trench retain the (original) oxide deposition.

[0086] The gate dielectric is formed by thermal oxide or RTO oxide orThermal SiN or thermal SiO_(x)N_(y) or by RTP SiN or by RTP SiO_(x)N_(y)or by JVC oxide, SiN, TiO₂ or TaO₂.

[0087] Referring now to FIG. 8, there is shown a cross section of gateelectrode after the layer of thick oxide 16 (FIG. 7) has been removed,dielectric 24 (FIG. 7) has also been removed. S/D 78 has implanted thesource/drain regions 76.

[0088]FIG. 9 shows a cross section of the gate electrode after theformation of silicide 82, the removal of spacers 64 (FIG. 8) and theimplant 84 of the lightly doped areas 86. It must be emphasized that thesecond embodiment of the invention results in having disposable spacer,an approach that greatly facilitates the LDD implant as will be clearfrom FIG. 9.

[0089]FIG. 9 shows the cross section of the completed gate electrodewithin the scope of the second embodiment of the present invention. Thesecond embodiment also results in a device with elevated source/drainregions while the channel implant has been achieved by means of aself-aligned channel implant. The advantages of the construct of thefirst embodiment as previously highlighted equally apply to the secondembodiment of the present invention.

[0090] Processing conditions for the steps of channel implant, theformation of LDD areas and spacer and the formation of the gatedielectric are, under the second embodiment of the invention,essentially the same as the conditions indicated for these processingsteps under the first embodiment of the invention.

[0091]FIGS. 10, 11, 12 and 13 show the third embodiment of the presentinvention. The processing steps as detailed under FIGS. 1 and 2 applyalso the third embodiment of the present invention, it is assumed thatthe explanations previously provided for FIG. 1 and FIG. 2 precede thefollowing explanations.

[0092] Processing conditions for the third embodiment will not befurther detailed in the following while it will be assumed that theseconditions are identical to the processing conditions as highlighted fora given process under the first two embodiments of the invention.

[0093] Referring now specifically to FIG. 10, there is shown a crosssection of the gate trench with a thin oxide layer 32 on the bottom ofthis trench. The channel implant 36 has been completed creating thechannel stop area 34 under the thin oxide layer 32.

[0094]FIG. 11 shows the formation of the spacer 42 on the sidewalls ofthe gate electrode and the formation of the gate electrode 46. Area 44under the gate electrode and where the gate electrode interfaces withthe silicon substrate is the gate dielectric. The corner areas 32 of thebottom of the trench remain in place as the previously deposited thinlayer of oxide.

[0095] It must be noted that the top of the gate spacers 42 have beenover-etched and, in so doing, been lowered in height to the point wherethe top of the spacers is lower than the top surface of the thick layerof oxide 42. This is important to note since this over-etching of thetop of the spacers 42 facilitates the formation of silicide at a laterstage in the process of the formation of the gate electrode. The topsurface of the gate poly is higher than the top of the gate spacers. Itmust further be noted that the trench etched into the surface of thesubstrate 10 is deeper than the trench etched under the first twoembodiments of the invention.

[0096]FIG. 12 shows the S/D implant 56 forming the S/D regions 54. Inthe areas 41, under the thin oxide layers 32 and under the gateelectrode spacers, LDD regions are formed by lateral diffusion of theS/D implant 56 around and under the vertical surface of the thin layer32 of oxide. This lateral diffusion replaces the previous step offorming the LDD regions.

[0097]FIG. 13 shows the formation 43 of silicide on the surface of thesilicon substrate above the S/D regions in addition to the formation ofsilicide on the top surface of the gate electrode.

[0098] While the present invention has been described with reference toillustrative embodiments, this description is not to be construed in alimiting sense. Various modifications and combinations, as well as otherembodiments of the invention reference to the description. It istherefore intended that the appended claims encompass any suchmodifications or embodiments.

What is claimed is:
 1. A method of forming a semiconductor for use witha gate electrode damascene process, comprising: providing asemiconductor silicon substrate; forming a thin dielectric layer on topof said substrate; depositing a thick layer of oxide on top of said thindielectric layer; creating a pattern said pattern to penetrate and gothrough said thick layer of oxide furthermore to penetrate and gothrough said thin dielectric layer furthermore to penetrate the surfaceof said silicon substrate; forming a thin layer of oxide at the bottomof said pattern; performing a channel implant in said silicon substratesaid implant to be self-aligned with said pattern said channel implantto penetrate said substrate to a depth between 0.02 and 1.5 um; formingLightly Doper Drain areas in said silicon substrate said LDD areas to beself-aligned with the extreme corners of said bottom of said pattern;forming a pocket implant in said silicon substrate said pocket implantto be self-aligned with said pattern; forming a spacer on the sidewallsof said pattern; removing said thin layer of oxide from the bottom ofsaid pattern where said thin layer of oxide is not covered by saidspacer; forming a gate dielectric at the bottom of said pattern wheresaid thin layer of oxide has been removed; forming a gate electrode insaid pattern; removing said thick layer of oxide from the top of saidthin dielectric layer; removing said thin dielectric layer from the topof said substrate; and performing source and drain implant in thesurface of said silicon substrate said implant to be substantiallyself-aligned with said with said pattern.
 2. The method of claim 1wherein said thin dielectric layer contains a thin layer of oxide withsaid thin layer of oxide having a thickness within the range of between20 and 500 Angstrom over which is deposited a layer of silicon nitridesaid layer of silicon nitride having a thickness within the range ofbetween 50 and 500 Angstrom said thin layer of oxide being a CVD oxidewhereby said thin oxide serves as a stress release between said siliconsubstrate and said layer of silicon nitride whereby further said layerof silicon nitride contains SiO_(x)N_(y) said layer of silicon nitridebeing deposited using a CVD process said layer of silicon nitrideserving as an etch stop layer.
 3. The method of claim 1 wherein saidthick layer of oxide is a layer with a thickness within the rangebetween 200 and 300 Angstrom said thick layer of oxide being depositedusing CVD or SOG techniques.
 4. The method of claim 1 wherein saidcreating a pattern is creating holes using the RIE etch process designedto create holes with vertical sidewalls whereby the width of said holesequals the width of the to be created gate electrode increased by twotimes the spacer width thereby allowing the creation of a spacersurrounding said gate electrode whereby furthermore said holes areetched through said oxide layer further etched through said dielectriclayer and further etched into the surface of said substrate therebyforming a shallow trench in the surface of said substrate.
 5. The methodof claim 1 wherein said creating a pattern is creating openings saidopenings to be wide in excess of 0.15 um whereby said openings have adepth within the range of between 100 and 1500 Angstrom.
 6. The methodof claim 1 whereby said thick layer of oxide is of a thickness such thatthe exposure applied for the formation of the Lightly Doped Drain areais deflected by said thick layer of oxide thereby not affecting thechannel implant region said not affecting said channel implant regionfurther emphasized by the angle of exposure for the formation of the LDDwhereby said LDD implant takes place under the extreme corners of thebottom of said pattern whereby furthermore said LDD implant isself-aligned with said pattern.
 7. The method of claim 1 wherein saidthin layer of oxide is created at the bottom of said holes therebycreating a surface where the gate dielectric will be formed whereby saidthin layer of oxide at the bottom of said pattern is created by wetoxidation at temperatures within the range of between 800 and 1200degrees C. for about between 2 and 4 hours thereby creating a oxidelayer within the range of between 0.8 and 1.0 um.
 8. The method of claim1 wherein said channel implant is the step of forming a self-alignedpunchthrough stopper into said semiconductor substrate said punchthroughstopper being essentially aligned with said pattern.
 9. The method ofclaim 1 whereby said forming a gate spacer comprises the thermallygrowing of a thin oxide on the sides of said gate electrode hole using ashort dry-oxidation process whereupon a conformal CVD oxide film isdeposited by decomposing TEOS at between 700 and 750 degrees C. followedby an anisotropic dry etch thereby leaving said spacers on the sidewallsof said gate electrode holes.
 10. The method of claim 1 wherein saidspacers are formed by a process including a substantially conformaldeposition within said trench of a spacer material selected from thegroup consisting of nitride, oxide, BSG, PSG and any combinationthereof, and a subsequent, substantially anisotropic etch of said spacermaterial.
 11. A method of forming a semiconductor for use with a gateelectrode damascene process, comprising: providing a semiconductorsilicon substrate; forming a thin dielectric layer on top of saidsubstrate; depositing a thick layer of oxide on top of said thindielectric layer; creating a pattern said pattern to penetrate and gothrough said thick layer of oxide furthermore to penetrate and gothrough said thin dielectric layer furthermore to penetrate the surfaceof said silicon substrate; forming a thin layer of oxide at the bottomof said pattern; forming a spacer on the sidewalls of said pattern;performing a channel implant in said silicon substrate said implant tobe self-aligned with said pattern wherein said channel implantpenetrates the surface of said substrate to a depth within the range ofbetween 0.02 and 1.5 um; removing said thin layer of oxide from thebottom of said pattern where said thin layer of oxide is not covered bysaid spacer; forming a gate dielectric at the bottom of said patternwhere said thin layer of oxide has been removed; forming a gateelectrode in said pattern; removing said thick layer of oxide from thetop of said thin dielectric layer; removing said thin dielectric layerfrom the top of said substrate; performing source and drain implant inthe surface of said silicon substrate said implant to be substantiallyself-aligned with said pattern; forming salicide on the surface of saidsilicon substrate above said source and drain implants and on the topsurface of said gate electrode; removing said spacer from the sidewallsof said pattern; and forming Lightly Doper Drain areas in said siliconsubstrate said LDD areas to be self-aligned with the extreme corners ofsaid bottom of said pattern.
 12. The method of claim 11 wherein saidthin dielectric layer contains a thin layer of oxide with said thinlayer of oxide having a thickness within the range of between 20 and 500Angstrom over which is deposited a layer of silicon nitride said layerof silicon nitride having a thickness within the range of between 50 and500 Angstrom said thin layer of oxide being a CVD oxide whereby saidthin oxide serves as a stress release between said silicon substrate andsaid layer of silicon nitride whereby further said layer of siliconnitride contains SiO_(x)N_(y) said layer of silicon nitride beingdeposited using a CVD process said layer of silicon nitride serving asan etch stop layer.
 13. The method of claim 11 wherein said thick layerof oxide is a layer with a thickness within the range between 200 and300 Angstrom said thick layer of oxide being deposited using CVD or SOGtechniques.
 14. The method of claim 11 wherein said creating a patternis creating holes using the RIE etch process designed to create holeswith vertical sidewalls whereby the width of said holes equals the widthof the to be created gate electrode increased by two times the spacerwidth thereby allowing the creation of a spacer surrounding said gateelectrode whereby furthermore said holes are etched through said oxidelayer further etched through said dielectric layer and further etchedinto the surface of said substrate thereby forming a shallow trench inthe surface of said substrate.
 15. The method of claim 11 wherein saidcreating a pattern is creating openings said openings to be wide inexcess of 0.15 um whereby said openings have a depth within the range ofbetween 100 and 1500 Angstrom.
 16. The method of claim 11 whereby saidthick layer of oxide is of a thickness such that the exposure appliedfor the formation of the Lightly Doped Drain area is deflected by saidthick layer of oxide thereby not affecting the channel implant regionsaid not affecting said channel implant region further emphasized by theangle of exposure for the formation of the LDD whereby said LDD implanttakes place under the extreme corners of the bottom of said patternwhereby furthermore said LDD implant is self-aligned with said pattern.17. The method of claim 11 wherein said thin layer of oxide is createdat the bottom of said holes thereby creating a surface where the gatedielectric will be formed.
 18. The method of claim 11 whereby saidforming a gate spacer comprises the thermally growing of a thin oxide onthe sides of said gate electrode hole using a short dry-oxidationprocess whereupon a conformal CVD oxide film is deposited by decomposingTEOS at between 700 and 750 degrees C. followed by an anisotropic dryetch thereby leaving said spacers on the sidewalls of said gateelectrode holes.
 19. The method of claim 11 wherein said spacers areformed by a process including a substantially conformal depositionwithin said trench of a spacer material selected from the groupconsisting of nitride, oxide, BSG, PSG and any combination thereof, anda subsequent, substantially anisotropic etch of said spacer material.20. A method of forming a semiconductor for use with a gate electrodedamascene process, comprising: providing a semiconductor siliconsubstrate; forming a thin dielectric layer on top of said substrate;depositing a thick layer of oxide on top of said thin dielectric layer;creating a pattern said pattern to penetrate and go through said thicklayer of oxide furthermore to penetrate and go through said thindielectric layer furthermore to penetrate the surface of said siliconsubstrate said penetration of said substrate to be to considerabledepth; forming a thin layer of oxide at the bottom of said pattern;performing a channel implant in said silicon substrate said implant tobe self-aligned with said pattern; forming a spacer on the sidewalls ofsaid pattern; removing said thin layer of oxide from the bottom of saidpattern where said thin layer of oxide is not covered by said spacer;forming a gate dielectric at the bottom of said pattern where said thinlayer of oxide has been removed; forming a gate electrode in saidpattern; removing said thick layer of oxide from the top of said thindielectric layer; removing said thin dielectric layer from the top ofsaid substrate; performing source and drain implant in the surface ofsaid silicon substrate said implant to be substantially self-alignedwith said with said pattern; and forming silicide on the surface of saidsilicon substrate above said source and drain implants and on the topsurface of said gate electrode.
 21. The method of claim 20 wherein saidthin dielectric layer contains: a thin layer of CVD oxide deposited oversaid substrate having a thickness between 20 and 500 Angstrom; and alayer of silicon nitride (SiO_(x)N_(y)) deposited over said thin layerof oxide having a thickness between 50 and 500 Angstrom said layer ofsilicon nitride being deposited using a CVD process.
 22. The method ofclaim 20 wherein said thick layer of oxide is a layer with a thicknesswithin the range between 200 and 300 Angstrom said thick layer of oxidebeing deposited using CVD or SOG techniques.
 23. The method of claim 20wherein said creating a pattern is creating holes using the RIE etchprocess designed to create holes with vertical sidewalls whereby thewidth of said holes equals the width of the to be created gate electrodeincreased by two times the spacer width thereby allowing the creation ofa spacer surrounding said gate electrode whereby furthermore said holesare etched through said oxide layer further etched through saiddielectric layer and further etched into the surface of said substratethereby forming a trench in the surface of said substrate.
 24. Themethod of claim 20 wherein said creating a pattern is creating openingssaid openings to be wide in excess of 0.15 um whereby said openings havea depth within the range of between 500 and 3000 Angstrom.
 25. Themethod of claim 20 whereby said thick layer of oxide is of a thicknesssuch that the exposure applied for the formation of the Lightly DopedDrain area is deflected by said thick layer of oxide thereby notaffecting the channel implant region said not affecting said channelimplant region further emphasized by the angle of exposure for theformation of the LDD whereby said LDD implant takes place under theextreme corners of the bottom of said pattern whereby furthermore saidLDD implant is self-aligned with said pattern.
 26. The method of claim20 wherein said spacer is formed using one of the group of processes ofthermal S_(i)N or CVD S_(i)N or thermal SiO_(x)N_(y) or CVD SiO_(x)N_(y)to a thickness within the range between 250 and 1500 Angstrom wherebythe top surface of said spacer is over-etched thereby reducing theheight of said spacer to below the top surface of the polysilicon of thegate electrode.
 27. The method of claim 20 whereby said forming a gatespacer comprises the thermally growing of a thin oxide on the sides ofsaid gate electrode hole using a short dry-oxidation process whereupon aconformal CVD oxide film is deposited by decomposing TEOS at between 700and 750 degrees C. followed by an anisotropic dry etch thereby leavingsaid spacers on the sidewalls of said gate electrode holes.
 28. Themethod of claim 20 wherein said spacers are formed by a processincluding a substantially conformal deposition within said trench of aspacer material selected from the group consisting of nitride, oxide,BSG, PSG and any combination thereof, and a subsequent, substantiallyanisotropic etch of said spacer material.